News and New Products

Gigabit talk dominates DesignCon (again)

By Maury Wright, Editor in Chief -- EDN, 2/8/2006

For at least the third consecutive year, 10-Gbps talk has dominated the DesignCon conference and exhibition. When the IT and data-communication segments will really move en masse toward 10-Gbps technologies remains unclear. But judging from the show this week, the PHY (physical layer) and MAC (media access controller) chips, the test-and-measurement gear, and the process technology needed to support 10-Gbps infrastructure are all ready.

Underneath, however, DesignCon is more about how things get done than about high-profile product announcements. That statement clearly fits the educational theme of the conference but also runs throughout the products and technologies on exhibit.

For instance, LSI Logic is featuring an ASIC communications chip in its booth, although the chip is actually the Ample Communications Redhawk IC: a two-port, 10-Gbps MAC chip announced last fall. LSI Logic not only builds the Redhawk IC, which is now in qualification, but also designed the XFI SerDes core that allows the chip to drive an XFP optical module. The core supports single-lane operation as fast as 11.1 Gbps, leaving sufficient margin for forward error correction in 10-Gbps designs.

The fast data paths discussed at DesignCon can also be found internal to systems in chip-to-chip, and board- or system-level interconnects. Coincident with the show, for instance, Xilinx announced that it is shipping its LogiCORE PCI Express IP core. Available in ×1, ×4, and ×8 flavors, LogiCORE has passed all PCI Express compliance testing administered at a recent PCI-SIG workshop, according to Xilinx.

Agilent Technologies, meanwhile, announced a PCI Express test suite for the 81250 Series Parallel Bit Error Rate Tester (ParBERT). The PCI Express suite offers one-button compliance testing but also offers the flexibility to support investigation of periodic jitter, random jitter, and bounded uncorrelated jitter stress generation. The company also announced a test suite for serial-gigabit receivers for the N4903A serial BERT.

SyntheSys Research also added to the capabilities of its BERTScope Option S product, which combines BERT capability with the eye-diagram diagnostics offered by sampling oscilloscopes. Option S, announced last year, added jitter measurement for stressed eye testing at speeds up to 10-Gbps. Now the company has added an application called the Jitter Template that automates jitter-stressed BER measurements. Again a partner, albeit a silent one, is involved; the company leveraged National Instruments' LabView graphical test language to develop the jitter-stressed application.

Finally, a number of companies at DesignCon are spinning process-technology stories. Fujitsu revealed details of its 65-nm roadmap, which it will utilize in both its 10-Gbps Ethernet switch chips and its WiMax SOC family. The company also recently announced plans for a 65-nm fab that will begin operation in 2007.

But not everyone is ready to blindly move down the sub-100-nm path. In a panel entitled "Why is EDA stagnating, or is it?" the conversation ended up revolving around the disconnect between trends in EDA consumption and chip design. During the panel, Len Perham, Chairman of the Board of Optimal Corp, repeatedly stated that, "0.11 micron [110 nm] is going to have a very long life." Indeed, as we pointed out in "Are cell-based ASICs going away?," finer process geometries no longer offer a sure path to faster speeds and low power due to the cost and risk of such designs. Perham noted that companies no longer see the typical motivation to move to 65- or 90-nm processes.