News and New Products

Next Headache: Variability

By Ed Sperling -- Electronic News, 2/7/2006

Variables used to be minor headaches for designers in the worst of cases, and occasionally catalysts for change in the best of cases. Increasingly, however, they’re looking like persistent migraines.

At 65 nanometers and beyond, variability is becoming a problem for everything from power to signal integrity. While many of these fluctuations never reached a level of concern at 90 nanometers and above, they are taking on a whole new dimension at process nodes where single atoms can and do make a difference.

“Variability increases as geometries shrink,” said Justin Rattner, CTO at Intel. “Leakage power varies five to 10 times. Frequency varies about 30 percent.”

He added that atomic errors can change the characteristics within a die. But predicting where that variability will occur, and what the effect will be is becoming more difficult. Instead of clean lines on a chart, Rattner said the new picture looks more like a blur and should be thought of in terms of probability rather than a fixed result.

Justin Rattner, CTO, Intel Corp.

Raul Camposano, CTO at Synopsys, said variables have always been present in design and manufacturing, but he added they were far more manageable at larger geometries.

“On the dynamic side, we are dealing with voltage variation, temperature variation and noise variation,” Camposano said. “Voltages are smaller and noise margins are smaller. Noise was not a part of timing analysis at 250 nanometers. At 90 and 65, it’s a must.”

However, he said that’s only part of the problem. Variability creeps into the process with everything from lithography to chemical mechanical planarization, as well as stress strain, which can change the electrical characteristics of the chip.

The CTO added that testing has to be integrated further and further into the design process. Speed testing was among the first additions. He said the next step will be to add parametric testing for a variety of functions on a chip.

“In EDA, timing tests are now normal,” Camposano said. “We need better models and more accurate models. You can go all the way to statistical timing analysis and statistical optimization.”

Raul Camposano, CTO, Synopsys

Industry sources predict that statistical timing — basically using probability to minimize the effects of any single source of variability — will become mainstream over the next year. IBM already has begun touting its statistical analysis capabilities to deal with variability. Other EDA vendors are expected to follow suit, with some announcements expected to start trickling out during the Design Automation Conference this summer.

And while these tools may help, they will do little to reduce the complexity — and final cost — of designing chips at advanced process nodes. Moore’s Law will march on for at least the next decade, but the cost of designing and producing chips will continue to grow proportionately.