Designing for Power

By Jessica Davis -- Electronic News, 2/6/2006

In days past, processor companies put the greatest focus on increasing performance by increasing the clock speed, but energy efficiency is becoming a dominant design factor in processor giant Intel’s chips as the company continues along the 2 year pace of scaling down to smaller process nodes.

That’s according to Justin Rattner, Intel’s CTO, in a keynote address at DesignCon 2006 in Santa Clara, Calif. on Monday, where he offered some insight into the company's efforts to increase the  energy efficiency of its processors. If Intel continued to scale at the current rate without addressing power issues, the results would be unacceptable, he said.

And as chips continue to scale down the company is seeing more variability among them, with frequency differences of as much as 30 percent and power leakage varying by 5 to 10 times.

In addition to the power concerns, heat is another practical issue that needs to be addressed.

“Thermal budgets are constrained by the market,” he said. “People are not willing to invest in the cooling systems needed for multi-hundred Watt processors."

Thermal environments are equally constrained on servers and desktop PCs as they are in mobile PCs, Rattner said, as end users are looking for smaller, quieter, cooler boxes for applications such as blade servers or living room-based entertainment PCs.

“We need to design our systems to fit within this set of thermal envelopes,” Rattner said.

With that in mind, Intel has developed several approaches to reduce leakage and heat.  Body bias can reduce leakage by 2 to 10 times, according to Rattner.  By using another technique, the stack effect, the company has realized between 5 and 10 times in leakage savings, although it has suffered a slight area penalty.

Justin Rattner, CTO, Intel Corp.

Another technique is to use sleep transistors to shut down a block of logic.  This can mean a reduction in leakage of 2 to 1000 times, Rattner said.

And yet another approach to reduce active power makes use of running multiple power supply rails through the chip with different rails delivering different wattages.  Rattner said Intel was delivering a paper on this approach at another event, the International Solid States Circuits Conference in San Francisco this week.

The paper describes using this approach to use two different power supplies on chip, one for the cache and another for the processor core.   This approach yielded a 35 percent reduction in power without any loss of performance, Rattner said.

Other innovations, designed to create more efficient overall platforms, are focusing on voltage regulators.  The company has created a fast CMOS voltage regulator that is 97 percent efficient compared to the 75 percent efficiency that today’s “garden variety” voltage regulators deliver, according to Rattner. But while the company has put most of the voltage regulators on chip, it has unable to integrate the inductors into CMOS.

Intel is also finding more opportunities for efficiency in layout changes, said Rattner.

“We are moving from a freelance era of layout and routing,” he said.  The new approach is more akin to a sea of transistors and will look more like ASIC and SoC designs, he added.

And in keeping with its new “platformization” strategy, Intel is moving its energy efficiency efforts beyond just the processor to the other chips it sells to create a full platform.

“A lot of work is going into looking at where power is going on the rest of the platform,” Rattner said. “We are looking to engineering power savings in chipsets.